// Copyright 2018 The Fuchsia Authors. All rights reserved.
// Use of this source code is governed by a BSD-style license that can be
// found in the LICENSE file.

#pragma once

#define AIU_958_BPF                             ((uint32_t)(0x00 << 2))
#define AIU_958_BRST                            ((uint32_t)(0x01 << 2))
#define AIU_958_LENGTH                          ((uint32_t)(0x02 << 2))
#define AIU_958_PADDSIZE                        ((uint32_t)(0x03 << 2))
#define AIU_958_MISC                            ((uint32_t)(0x04 << 2))
#define AIU_958_FORCE_LEFT                      ((uint32_t)(0x05 << 2))
#define AIU_958_DISCARD_NUM                     ((uint32_t)(0x06 << 2))
#define AIU_958_DCU_FF_CTRL                     ((uint32_t)(0x07 << 2))
#define AIU_958_CHSTAT_L0                       ((uint32_t)(0x08 << 2))
#define AIU_958_CHSTAT_L1                       ((uint32_t)(0x09 << 2))
#define AIU_958_CTRL                            ((uint32_t)(0x0A << 2))
#define AIU_958_RPT                             ((uint32_t)(0x0B << 2))
#define AIU_I2S_MUTE_SWAP                       ((uint32_t)(0x0C << 2))
#define AIU_I2S_SOURCE_DESC                     ((uint32_t)(0x0D << 2))
#define AIU_I2S_MED_CTRL                        ((uint32_t)(0x0E << 2))
#define AIU_I2S_MED_THRESH                      ((uint32_t)(0x0F << 2))
#define AIU_I2S_DAC_CFG                         ((uint32_t)(0x10 << 2))
#define AIU_I2S_MISC                            ((uint32_t)(0x12 << 2))
#define AIU_I2S_OUT_CFG                         ((uint32_t)(0x13 << 2))
#define AIU_RST_SOFT                            ((uint32_t)(0x15 << 2))
#define AIU_CLK_CTRL                            ((uint32_t)(0x16 << 2))
#define AIU_MIX_ADCCFG                          ((uint32_t)(0x17 << 2))
#define AIU_MIX_CTRL                            ((uint32_t)(0x18 << 2))
#define AIU_CLK_CTRL_MORE                       ((uint32_t)(0x19 << 2))
#define AIU_958_POP                             ((uint32_t)(0x1A << 2))
#define AIU_MIX_GAIN                            ((uint32_t)(0x1B << 2))
#define AIU_958_SYNWORD1                        ((uint32_t)(0x1C << 2))
#define AIU_958_SYNWORD2                        ((uint32_t)(0x1D << 2))
#define AIU_958_SYNWORD3                        ((uint32_t)(0x1E << 2))
#define AIU_958_SYNWORD1_MASK                   ((uint32_t)(0x1F << 2))
#define AIU_958_SYNWORD2_MASK                   ((uint32_t)(0x20 << 2))
#define AIU_958_SYNWORD3_MASK                   ((uint32_t)(0x21 << 2))
#define AIU_958_FFRDOUT_THD                     ((uint32_t)(0x22 << 2))
#define AIU_958_LENGTH_PER_PAUSE                ((uint32_t)(0x23 << 2))
#define AIU_958_PAUSE_NUM                       ((uint32_t)(0x24 << 2))
#define AIU_958_PAUSE_PAYLOAD                   ((uint32_t)(0x25 << 2))
#define AIU_958_AUTO_PAUSE                      ((uint32_t)(0x26 << 2))
#define AIU_958_PAUSE_PD_LENGTH                 ((uint32_t)(0x27 << 2))
#define AIU_CODEC_DAC_LRCLK_CTRL                ((uint32_t)(0x28 << 2))
#define AIU_CODEC_ADC_LRCLK_CTRL                ((uint32_t)(0x29 << 2))
#define AIU_HDMI_CLK_DATA_CTRL                  ((uint32_t)(0x2a << 2))
#define AIU_CODEC_CLK_DATA_CTRL                 ((uint32_t)(0x2b << 2))
#define AIU_958_CHSTAT_R0                       ((uint32_t)(0x30 << 2))
#define AIU_958_CHSTAT_R1                       ((uint32_t)(0x31 << 2))
#define AIU_958_VALID_CTRL                      ((uint32_t)(0x32 << 2))
#define AIU_AIFIFO2_CTRL                        ((uint32_t)(0x40 << 2))
#define AIU_AIFIFO2_STATUS                      ((uint32_t)(0x41 << 2))
#define AIU_AIFIFO2_GBIT                        ((uint32_t)(0x42 << 2))
#define AIU_AIFIFO2_CLB                         ((uint32_t)(0x43 << 2))
#define AIU_CRC_CTRL                            ((uint32_t)(0x44 << 2))
#define AIU_CRC_STATUS                          ((uint32_t)(0x45 << 2))
#define AIU_CRC_SHIFT_REG                       ((uint32_t)(0x46 << 2))
#define AIU_CRC_IREG                            ((uint32_t)(0x47 << 2))
#define AIU_CRC_CAL_REG1                        ((uint32_t)(0x48 << 2))
#define AIU_CRC_CAL_REG0                        ((uint32_t)(0x49 << 2))
#define AIU_CRC_POLY_COEF1                      ((uint32_t)(0x4a << 2))
#define AIU_CRC_POLY_COEF0                      ((uint32_t)(0x4b << 2))
#define AIU_CRC_BIT_SIZE1                       ((uint32_t)(0x4c << 2))
#define AIU_CRC_BIT_SIZE0                       ((uint32_t)(0x4d << 2))
#define AIU_CRC_BIT_CNT1                        ((uint32_t)(0x4e << 2))
#define AIU_CRC_BIT_CNT0                        ((uint32_t)(0x4f << 2))
#define AIU_AMCLK_GATE_HI                       ((uint32_t)(0x50 << 2))
#define AIU_AMCLK_GATE_LO                       ((uint32_t)(0x51 << 2))
#define AIU_AMCLK_MSR                           ((uint32_t)(0x52 << 2))
#define AIU_MEM_I2S_START_PTR                   ((uint32_t)(0x60 << 2))
#define AIU_MEM_I2S_RD_PTR                      ((uint32_t)(0x61 << 2))
#define AIU_MEM_I2S_END_PTR                     ((uint32_t)(0x62 << 2))
#define AIU_MEM_I2S_MASKS                       ((uint32_t)(0x63 << 2))
#define AIU_MEM_I2S_CONTROL                     ((uint32_t)(0x64 << 2))
#define AIU_MEM_IEC958_START_PTR                ((uint32_t)(0x65 << 2))
#define AIU_MEM_IEC958_RD_PTR                   ((uint32_t)(0x66 << 2))
#define AIU_MEM_IEC958_END_PTR                  ((uint32_t)(0x67 << 2))
#define AIU_MEM_IEC958_MASKS                    ((uint32_t)(0x68 << 2))
#define AIU_MEM_IEC958_CONTROL                  ((uint32_t)(0x69 << 2))
#define AIU_MEM_AIFIFO2_START_PTR               ((uint32_t)(0x6a << 2))
#define AIU_MEM_AIFIFO2_CURR_PTR                ((uint32_t)(0x6b << 2))
#define AIU_MEM_AIFIFO2_END_PTR                 ((uint32_t)(0x6c << 2))
#define AIU_MEM_AIFIFO2_BYTES_AVAIL             ((uint32_t)(0x6d << 2))
#define AIU_MEM_AIFIFO2_CONTROL                 ((uint32_t)(0x6e << 2))
#define AIU_MEM_AIFIFO2_MAN_WP                  ((uint32_t)(0x6f << 2))
#define AIU_MEM_AIFIFO2_MAN_RP                  ((uint32_t)(0x70 << 2))
#define AIU_MEM_AIFIFO2_LEVEL                   ((uint32_t)(0x71 << 2))
#define AIU_MEM_AIFIFO2_BUF_CNTL                ((uint32_t)(0x72 << 2))
#define AIU_MEM_I2S_MAN_WP                      ((uint32_t)(0x73 << 2))
#define AIU_MEM_I2S_MAN_RP                      ((uint32_t)(0x74 << 2))
#define AIU_MEM_I2S_LEVEL                       ((uint32_t)(0x75 << 2))
#define AIU_MEM_I2S_BUF_CNTL                    ((uint32_t)(0x76 << 2))
#define AIU_MEM_I2S_BUF_WRAP_COUNT              ((uint32_t)(0x77 << 2))
#define AIU_MEM_I2S_MEM_CTL                     ((uint32_t)(0x78 << 2))
#define AIU_MEM_IEC958_MEM_CTL                  ((uint32_t)(0x79 << 2))
#define AIU_MEM_IEC958_WRAP_COUNT               ((uint32_t)(0x7a << 2))
#define AIU_MEM_IEC958_IRQ_LEVEL                ((uint32_t)(0x7b << 2))
#define AIU_MEM_IEC958_MAN_WP                   ((uint32_t)(0x7c << 2))
#define AIU_MEM_IEC958_MAN_RP                   ((uint32_t)(0x7d << 2))
#define AIU_MEM_IEC958_LEVEL                    ((uint32_t)(0x7e << 2))
#define AIU_MEM_IEC958_BUF_CNTL                 ((uint32_t)(0x7f << 2))
#define AIU_AIFIFO_CTRL                         ((uint32_t)(0x80 << 2))
#define AIU_AIFIFO_STATUS                       ((uint32_t)(0x81 << 2))
#define AIU_AIFIFO_GBIT                         ((uint32_t)(0x82 << 2))
#define AIU_AIFIFO_CLB                          ((uint32_t)(0x83 << 2))
#define AIU_MEM_AIFIFO_START_PTR                ((uint32_t)(0x84 << 2))
#define AIU_MEM_AIFIFO_CURR_PTR                 ((uint32_t)(0x85 << 2))
#define AIU_MEM_AIFIFO_END_PTR                  ((uint32_t)(0x86 << 2))
#define AIU_MEM_AIFIFO_BYTES_AVAIL              ((uint32_t)(0x87 << 2))
#define AIU_MEM_AIFIFO_CONTROL                  ((uint32_t)(0x88 << 2))
#define AIU_MEM_AIFIFO_MAN_WP                   ((uint32_t)(0x89 << 2))
#define AIU_MEM_AIFIFO_MAN_RP                   ((uint32_t)(0x8a << 2))
#define AIU_MEM_AIFIFO_LEVEL                    ((uint32_t)(0x8b << 2))
#define AIU_MEM_AIFIFO_BUF_CNTL                 ((uint32_t)(0x8c << 2))
#define AIU_MEM_AIFIFO_BUF_WRAP_COUNT           ((uint32_t)(0x8d << 2))
#define AIU_MEM_AIFIFO2_BUF_WRAP_COUNT          ((uint32_t)(0x8e << 2))
#define AIU_MEM_AIFIFO_MEM_CTL                  ((uint32_t)(0x8f << 2))
#define AIU_AIFIFO_TIME_STAMP_CNTL              ((uint32_t)(0x90 << 2))
#define AIU_AIFIFO_TIME_STAMP_SYNC_0            ((uint32_t)(0x91 << 2))
#define AIU_AIFIFO_TIME_STAMP_SYNC_1            ((uint32_t)(0x92 << 2))
#define AIU_AIFIFO_TIME_STAMP_0                 ((uint32_t)(0x93 << 2))
#define AIU_AIFIFO_TIME_STAMP_1                 ((uint32_t)(0x94 << 2))
#define AIU_AIFIFO_TIME_STAMP_2                 ((uint32_t)(0x95 << 2))
#define AIU_AIFIFO_TIME_STAMP_3                 ((uint32_t)(0x96 << 2))
#define AIU_AIFIFO_TIME_STAMP_LENGTH            ((uint32_t)(0x97 << 2))
#define AIU_AIFIFO2_TIME_STAMP_CNTL             ((uint32_t)(0x98 << 2))
#define AIU_AIFIFO2_TIME_STAMP_SYNC_0           ((uint32_t)(0x99 << 2))
#define AIU_AIFIFO2_TIME_STAMP_SYNC_1           ((uint32_t)(0x9a << 2))
#define AIU_AIFIFO2_TIME_STAMP_0                ((uint32_t)(0x9b << 2))
#define AIU_AIFIFO2_TIME_STAMP_1                ((uint32_t)(0x9c << 2))
#define AIU_AIFIFO2_TIME_STAMP_2                ((uint32_t)(0x9d << 2))
#define AIU_AIFIFO2_TIME_STAMP_3                ((uint32_t)(0x9e << 2))
#define AIU_AIFIFO2_TIME_STAMP_LENGTH           ((uint32_t)(0x9f << 2))
#define AIU_IEC958_TIME_STAMP_CNTL              ((uint32_t)(0xa0 << 2))
#define AIU_IEC958_TIME_STAMP_SYNC_0            ((uint32_t)(0xa1 << 2))
#define AIU_IEC958_TIME_STAMP_SYNC_1            ((uint32_t)(0xa2 << 2))
#define AIU_IEC958_TIME_STAMP_0                 ((uint32_t)(0xa3 << 2))
#define AIU_IEC958_TIME_STAMP_1                 ((uint32_t)(0xa4 << 2))
#define AIU_IEC958_TIME_STAMP_2                 ((uint32_t)(0xa5 << 2))
#define AIU_IEC958_TIME_STAMP_3                 ((uint32_t)(0xa6 << 2))
#define AIU_IEC958_TIME_STAMP_LENGTH            ((uint32_t)(0xa7 << 2))
#define AIU_MEM_AIFIFO2_MEM_CTL                 ((uint32_t)(0xa8 << 2))
#define AIU_I2S_CBUS_DDR_CNTL                   ((uint32_t)(0xa9 << 2))
#define AIU_I2S_CBUS_DDR_WDATA                  ((uint32_t)(0xaa << 2))
#define AIU_I2S_CBUS_DDR_ADDR                   ((uint32_t)(0xab << 2))

#define AIU_REG_MASK(bits)                      ((uint32_t)((1u << (bits)) - 1))

// Bitfield defs for the IEC958 Misc reg (0x04)
#define AIU_958_MISC_NON_PCM                    ((uint32_t)(1u << 0))
#define AIU_958_MISC_16BIT                      ((uint32_t)(1u << 1))
#define AIU_958_MISC_INVERT_MSB                 ((uint32_t)(1u << 2))
#define AIU_958_MISC_EXTEND_MSB                 ((uint32_t)(1u << 3))
#define AIU_958_MISC_TX_MSB_FIRST               ((uint32_t)(1u << 4))
#define AIU_958_MISC_16BIT_ALIGN_MASK           AIU_REG_MASK(2)
#define AIU_958_MISC_16BIT_ALIGN_SHIFT          ((uint32_t)(5u))
#define AIU_958_MISC_32BIT_MODE                 ((uint32_t)(1u << 7))
#define AIU_958_MISC_32BIT_SHIFT_MASK           AIU_REG_MASK(3)
#define AIU_958_MISC_32BIT_SHIFT_SHIFT          ((uint32_t)8u)
#define AIU_958_MISC_BIG_ENDIAN                 ((uint32_t)(1u << 11))
#define AIU_958_MISC_STREAM_USER_DATA           ((uint32_t)(1u << 12))
#define AIU_958_MISC_FORCE_LR                   ((uint32_t)(1u << 13))
#define AIU_958_MISC_PCM_SAMP_CTRL_MASK         AIU_REG_MASK(2)
#define AIU_958_MISC_PCM_SAMP_CTRL_SHIFT        ((uint32_t)14u)

// Constants for the Misc alignment field.
// RIGHT:  16 bit samples are transmitted as (00000000b | Sample)
// CENTER: 16 bit samples are transmitted as (0000b | Sample | 0000b)
// LEFT:   16 bit samples are transmitted as (Sample | 00000000b)
#define AIU_958_MISC_16BIT_ALIGN_RIGHT          ((uint32_t)0x00)
#define AIU_958_MISC_16BIT_ALIGN_CENTER         ((uint32_t)0x01)
#define AIU_958_MISC_16BIT_ALIGN_LEFT           ((uint32_t)0x02)

// Constants for the Misc PCM sample control field.
#define AIU_958_MISC_PCM_SAMP_CTRL_NO_SAMPLE    ((uint32_t)0x00)
#define AIU_958_MISC_PCM_SAMP_CTRL_UP           ((uint32_t)0x01)
#define AIU_958_MISC_PCM_SAMP_CTRL_DOWN         ((uint32_t)0x02)
#define AIU_958_MISC_PCM_SAMP_CTRL_DOWN_DROP    ((uint32_t)0x03)

// Bitfield defs for the IEC958 FIFO control reg (0x07)
#define AIU_958_DCU_FF_CTRL_ENB                 ((uint32_t)(1u << 0))
#define AIU_958_DCU_FF_CTRL_AUTO_DISABLE        ((uint32_t)(1u << 1))
#define AIU_958_DCU_FF_CTRL_IRQ_MODE_MASK       AIU_REG_MASK(2u)
#define AIU_958_DCU_FF_CTRL_IRQ_MODE_SHIFT      ((uint32_t)2u)
#define AIU_958_DCU_FF_CTRL_SYNC_HEAD_SEEK_ENB  ((uint32_t)(1u << 4))
#define AIU_958_DCU_FF_CTRL_BYTE_SEEK_ENB       ((uint32_t)(1u << 5))
#define AIU_958_DCU_FF_CTRL_CONT_SEEK           ((uint32_t)(1u << 6))
#define AIU_958_DCU_FF_CTRL_8BIT                ((uint32_t)(1u << 7))
#define AIU_958_DCU_FF_CTRL_FIFO_CNT_MASK       AIU_REG_MASK(8u)
#define AIU_958_DCU_FF_CTRL_FIFO_CNT_SHIFT      ((uint32_t)8u)

// Bitfield defs for the IEC958 control reg (0x0A)
#define AIU_958_CTRL_HOLD_INTERFACE             ((uint32_t)(1u << 0))
#define AIU_958_CTRL_SWAP_CHAN_MASK             AIU_REG_MASK(2u)
#define AIU_958_CTRL_SWAP_CHAN_SHIFT            ((uint32_t)1u)
#define AIU_958_CTRL_MUTE_RIGHT                 ((uint32_t)(1u << 3))
#define AIU_958_CTRL_MUTE_LEFT                  ((uint32_t)(1u << 4))
#define AIU_958_CTRL_MUTE_CONSTANT_MASK         AIU_REG_MASK(3u)
#define AIU_958_CTRL_MUTE_CONSTANT_SHIFT        ((uint32_t)5u)
#define AIU_958_CTRL_FUB_MASK                   AIU_REG_MASK(2u)
#define AIU_958_CTRL_FUB_SHIFT                  ((uint32_t)8u)

// Constants for the MUTE_CONSTANT field of the 958_CTRL register
// ZERO:        0x000000
// 24BIT_UZERO: 0x800000
// 20BIT_UZERO: 0x080000
// 16BIT_UZERO: 0x008000
// 24BIT_ONE:   0x000001
// 20BIT_ONE:   0x000010
// 16BIT_ONE:   0x000100
#define AIU_958_CTRL_MC_ZERO                    ((uint32_t)0u)
#define AIU_958_CTRL_MC_24BIT_UZERO             ((uint32_t)1u)
#define AIU_958_CTRL_MC_20BIT_UZERO             ((uint32_t)2u)
#define AIU_958_CTRL_MC_16BIT_UZERO             ((uint32_t)3u)
#define AIU_958_CTRL_MC_24BIT_ONE               ((uint32_t)4u)
#define AIU_958_CTRL_MC_20BIT_ONE               ((uint32_t)5u)
#define AIU_958_CTRL_MC_16BIT_ONE               ((uint32_t)6u)

// Constants for the FIFO underrun behavior (FUB) field of the 958_CTRL register
// ZERO          : fill with 0x000000
// MUTE_CONSTANT : fill with the selected mute constant
// REPEAT_LAST   : repeat the last LR frame
#define AIU_958_CTRL_FUB_ZERO                   ((uint32_t)0u)
#define AIU_958_CTRL_FUB_MUTE_CONSTANT          ((uint32_t)1u)
#define AIU_958_CTRL_FUB_REPEAT_LAST            ((uint32_t)2u)

// Bitfield defs for RST_SOFT (0x15)
#define AIU_RS_I2S_FAST_DOMAIN                  ((uint32_t)(1u << 0))
#define AIU_RS_I2S_SLOW_DOMAIN                  ((uint32_t)(1u << 1))
#define AIU_RS_958_FAST_DOMAIN                  ((uint32_t)(1u << 2))
#define AIU_RS_958_SLOW_DOMAIN                  ((uint32_t)(1u << 3))

// Bitfield defs for CLK_CTRL (0x16)
#define AIU_CLK_CTRL_ENB_I2S_DIV                ((uint32_t)(1u << 0))
#define AIU_CLK_CTRL_ENB_958_DIV                ((uint32_t)(1u << 1))
#define AIU_CLK_CTRL_I2S_DIV_MASK               AIU_REG_MASK(2u)
#define AIU_CLK_CTRL_I2S_DIV_SHIFT              ((uint32_t)2u)
#define AIU_CLK_CTRL_958_DIV_MASK               AIU_REG_MASK(2u)
#define AIU_CLK_CTRL_958_DIV_SHIFT              ((uint32_t)4u)
#define AIU_CLK_CTRL_INV_AO_CLK                 ((uint32_t)(1u << 6))
#define AIU_CLK_CTRL_INV_ALR_CLK                ((uint32_t)(1u << 7))
#define AIU_CLK_CTRL_ALR_SKEW_MASK              AIU_REG_MASK(2u)
#define AIU_CLK_CTRL_ALR_SKEW_SHIFT             ((uint32_t)8u)
#define AIU_CLK_CTRL_CLK_SOURCE_SEL             ((uint32_t)(1u << 10))
#define AIU_CLK_CTRL_AMCLK_OUT_DIV              ((uint32_t)(1u << 11))
#define AIU_CLK_CTRL_958_DIV_MORE               ((uint32_t)(1u << 12))
#define AIU_CLK_CTRL_958_DIV_MORE               ((uint32_t)(1u << 12))
#define AIU_CLK_CTRL_PA_ADDR_SEL_MASK           AIU_REG_MASK(2u)
#define AIU_CLK_CTRL_PA_ADDR_SEL_SHIFT          ((uint32_t)13u)
#define AIU_CLK_CTRL_ENB_DDR_ARB                ((uint32_t)(1u << 15))

// Constants for the ALR Clk skew field
// SAME_TIME: ALR clk transitions as the MSB is sent
// BEFORE:    ALR clk transitions 1 cycle before the MSB is sent
// AFTER:     ALR clk transitions 1 cycle after the MSB is sent
#define AIU_CLK_CTRL_ALR_SKEW_SAME_TIME         ((uint32_t)0x00)
#define AIU_CLK_CTRL_ALR_SKEW_BEFORE            ((uint32_t)0x01)
#define AIU_CLK_CTRL_ALR_SKEW_AFTER             ((uint32_t)0x02)

// Constants for the Parser-A Addr Select field
#define AIU_CLK_CTRL_PAAS_AFIFO2                ((uint32_t)0x00)
#define AIU_CLK_CTRL_PAAS_IEC958                ((uint32_t)0x01)
#define AIU_CLK_CTRL_PAAS_AFIFO                 ((uint32_t)0x02)
#define AIU_CLK_CTRL_PAAS_I2S                   ((uint32_t)0x03)

// Bitfield defs for the Valid register (0x32)
#define AIU_958_VCTRL_VBIT                      ((uint32_t)(1u << 0))
#define AIU_958_VCTRL_SEND_VBIT                 ((uint32_t)(1u << 1))

// Bitfield defs for the IEC958 Masks reg (0x68)
#define AIU_MEM_IEC958_MASKS_CHAN_RD_MASK       AIU_REG_MASK(8)
#define AIU_MEM_IEC958_MASKS_CHAN_RD_SHIFT      ((uint32_t)0u)
#define AIU_MEM_IEC958_MASKS_CHAN_MEM_MASK      AIU_REG_MASK(8)
#define AIU_MEM_IEC958_MASKS_CHAN_MEM_SHIFT     ((uint32_t)8u)

// Bitfield defs for the IEC958 Mem Control reg (0x69)
#define AIU_958_MCTRL_INIT                      ((uint32_t)(1u << 0))
#define AIU_958_MCTRL_FILL_ENB                  ((uint32_t)(1u << 1))
#define AIU_958_MCTRL_EMPTY_ENB                 ((uint32_t)(1u << 2))
#define AIU_958_MCTRL_ENDIAN_MASK               AIU_REG_MASK(3)
#define AIU_958_MCTRL_ENDIAN_SHIFT              ((uint32_t)3u)
#define AIU_958_MCTRL_RD_DDR                    ((uint32_t)(1u << 6))
#define AIU_958_MCTRL_16BIT_MODE                ((uint32_t)(1u << 7))
#define AIU_958_MCTRL_LINEAR_RAW                ((uint32_t)(1u << 8))
#define AIU_958_MCTRL_ENDIAN_JIC                ((uint32_t)(1u << 9))
#define AIU_958_MCTRL_FETCHING_DDR              ((uint32_t)(1u << 10))
#define AIU_958_MCTRL_FIFO_HAS_DATA             ((uint32_t)(1u << 11))
#define AIU_958_MCTRL_USE_LEVEL                 ((uint32_t)(1u << 12))
#define AIU_958_MCTRL_SIM_ENB                   ((uint32_t)(1u << 13))
#define AIU_958_MCTRL_RD_DATA_BASE_BEGIN_MASK   AIU_REG_MASK(4)
#define AIU_958_MCTRL_RD_DATA_BASE_BEGIN_SHIFT  ((uint32_t)24u)
#define AIU_958_MCTRL_CH_ALWAYS_8               ((uint32_t)(1u << 30))
#define AIU_958_MCTRL_A_URGENT                  ((uint32_t)(1u << 31))

// Bitfield defs for the IEC958 Buf Control reg (0x7f)
#define AIU_958_BCTRL_LEVEL_HOLD_MASK           AIU_REG_MASK(16)
#define AIU_958_BCTRL_LEVEL_HOLD_SHIFT          ((uint32_t)0u)
#define AIU_958_BCTRL_A_ID_MASK                 AIU_REG_MASK(6)
#define AIU_958_BCTRL_A_ID_SHIFT                ((uint32_t)16u)
#define AIU_958_BCTRL_A_BRST_NUM_MASK           AIU_REG_MASK(6)
#define AIU_958_BCTRL_A_BRST_NUM_SHIFT          ((uint32_t)22u)

// Flags that can be set in the low 32 bits a SPDIF channel status word.  Note,
// these do not have anything specific to do with AmLogic audio units, but it is
// as good a place as any to put some definitions.
//
// See
// https://en.wikipedia.org/wiki/S/PDIF
// http://www.av-iq.com/avcat/images/documents/pdfs/digaudiochannelstatusbits.pdf
// http://www.minidisc.org/spdif_c_channel.html
// https://hackaday.io/project/24911-propeller-spdif-receiver/details
// For some publicly available details about the meaning of these bits
//
#define SPDIF_CS_SPDIF_CONSUMER                 ((uint32_t)(0u << 0))
#define SPDIF_CS_AES_PRO                        ((uint32_t)(1u << 0))
#define SPDIF_CS_AUD_DATA_PCM                   ((uint32_t)(0u << 1))
#define SPDIF_CS_AUD_DATA_NON_PCM               ((uint32_t)(1u << 1))
#define SPDIF_CS_COPY_DENIED                    ((uint32_t)(0u << 2))
#define SPDIF_CS_COPY_PERMITTED                 ((uint32_t)(1u << 2))
#define SPDIF_CS_NO_PRE_EMPHASIS                ((uint32_t)(0u << 3))
#define SPDIF_CS_PRE_EMPHASIS                   ((uint32_t)(1u << 3))
#define SPDIF_CS_CHAN_MODE_0                    ((uint32_t)(0u << 6))
#define SPDIF_CS_CCODE(g, c)                    ((uint32_t)(((g & 0x7) << 8) | ((c & 0xf) << 11)))
#define SPDIF_CS_L_BIT                          ((uint32_t)(1u << 15))
#define SPDIF_CS_SRC_NUM(N)                     ((uint32_t)((N & 0xf) << 16))
#define SPDIF_CS_CHAN_NUM(N)                    ((uint32_t)((N & 0xf) << 20))
#define SPDIF_CS_SAMP_FREQ_IGNORE               ((uint32_t)(0x1 << 24))
#define SPDIF_CS_SAMP_FREQ_22_05K               ((uint32_t)(0x4 << 24))
#define SPDIF_CS_SAMP_FREQ_44_1K                ((uint32_t)(0x0 << 24))
#define SPDIF_CS_SAMP_FREQ_88_2K                ((uint32_t)(0x8 << 24))
#define SPDIF_CS_SAMP_FREQ_176_4K               ((uint32_t)(0xC << 24))
#define SPDIF_CS_SAMP_FREQ_24K                  ((uint32_t)(0x6 << 24))
#define SPDIF_CS_SAMP_FREQ_32K                  ((uint32_t)(0x3 << 24))
#define SPDIF_CS_SAMP_FREQ_48K                  ((uint32_t)(0x2 << 24))
#define SPDIF_CS_SAMP_FREQ_96K                  ((uint32_t)(0xA << 24))
#define SPDIF_CS_SAMP_FREQ_192K                 ((uint32_t)(0xE << 24))
#define SPDIF_CS_CLK_ACC_100PPM                 ((uint32_t)(0 << 28))
#define SPDIF_CS_CLK_ACC_VARIABLE               ((uint32_t)(1 << 28))
#define SPDIF_CS_CLK_ACC_50PPM                  ((uint32_t)(2 << 28))

#define SPDIF_CS_CCODE_GENERAL                  SPDIF_CS_CCODE(0, 0)
#define SPDIF_CS_CCODE_SOLID_STATE_RECORDER     SPDIF_CS_CCODE(0, 1)
#define SPDIF_CS_CCODE_EXPERIMENTAL             SPDIF_CS_CCODE(0, 8)

#define SPDIF_CS_CCODE_CD                       SPDIF_CS_CCODE(1, 0)
#define SPDIF_CS_CCODE_LASERDISC                SPDIF_CS_CCODE(1, 1)
#define SPDIF_CS_CCODE_MINIDISC                 SPDIF_CS_CCODE(1, 3)
#define SPDIF_CS_CCODE_DVD                      SPDIF_CS_CCODE(1, 9)

#define SPDIF_CS_CCODE_PCM_CODEC                SPDIF_CS_CCODE(2, 0)
#define SPDIF_CS_CCODE_DIGITAL_SAMPLER          SPDIF_CS_CCODE(2, 2)
#define SPDIF_CS_CCODE_DIGITAL_MIXER            SPDIF_CS_CCODE(2, 3)
#define SPDIF_CS_CCODE_DIGITAL_PROCESSOR        SPDIF_CS_CCODE(2, 4)
#define SPDIF_CS_CCODE_SAMPLE_RATE_CONVERTER    SPDIF_CS_CCODE(2, 5)

#define SPDIF_CS_CCODE_DAT                      SPDIF_CS_CCODE(3, 0)
#define SPDIF_CS_CCODE_DCC                      SPDIF_CS_CCODE(3, 1)
#define SPDIF_CS_CCODE_VCR                      SPDIF_CS_CCODE(3, 8)

#define SPDIF_CS_CCODE_DBR_JAPAN                SPDIF_CS_CCODE(4, 0)
#define SPDIF_CS_CCODE_SW_DELIVERY_INTF         SPDIF_CS_CCODE(4, 1)
#define SPDIF_CS_CCODE_DBR_USA                  SPDIF_CS_CCODE(4, 8)
#define SPDIF_CS_CCODE_DBR_EUROPE               SPDIF_CS_CCODE(4, 12)

#define SPDIF_CS_CCODE_SYNTHESIZER              SPDIF_CS_CCODE(5, 0)
#define SPDIF_CS_CCODE_MICROPHONE               SPDIF_CS_CCODE(5, 1)

#define SPDIF_CS_CCODE_A2D_CONVERTER            SPDIF_CS_CCODE(6, 0)
#define SPDIF_CS_CCODE_A2D_CONVERTER_WITH_SCMS  SPDIF_CS_CCODE(6, 2)

